
\subsection{uDMA I2C0 Registers}
{\small
\begin{tabularx}{\textwidth}{|l|l|l|l|l|l|X|}
  \hline
  \textbf{Name} & \textbf{Address}  & \textbf{Size} & \textbf{Type} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
  \hline
  RX\_SADDR & \texttt{0x1A102180} & 32 & Config & R/W & \texttt{0x00000000} & uDMA RX I2C buffer base address configuration register.\\
  \hline
  RX\_SIZE & \texttt{0x1A102184} & 32 & Config & R/W & \texttt{0x00000000} & uDMA RX I2C buffer size configuration register.\\
  \hline
  RX\_CFG & \texttt{0x1A102188} & 32 & Config & R/W & \texttt{0x00000000} & uDMA RX I2C stream configuration register.\\
  \hline
  TX\_SADDR & \texttt{0x1A102190} & 32 & Config & R/W & \texttt{0x00000000} & uDMA TX I2C buffer base address configuration register.\\
  \hline
  TX\_SIZE & \texttt{0x1A102194} & 32 & Config & R/W & \texttt{0x00000000} & uDMA TX I2C buffer size configuration register.\\
  \hline
  TX\_CFG & \texttt{0x1A102198} & 32 & Config & R/W & \texttt{0x00000000} & uDMA TX I2C stream configuration register.\\
  \hline
  CMD\_SADDR & \texttt{0x1A1021A0} & 32 & Config & R/W & \texttt{0x00000000} & uDMA CMD I2C buffer base address configuration register.\\
  \hline
  CMD\_SIZE & \texttt{0x1A1021A4} & 32 & Config & R/W & \texttt{0x00000000} & uDMA CMD I2C buffer size configuration register.\\
  \hline
  CMD\_CFG & \texttt{0x1A1021A8} & 32 & Config & R/W & \texttt{0x00000000} & uDMA CMD I2C stream configuration register.\\
  \hline
  STATUS & \texttt{0x1A1021B0} & 32 & Status & R/W & \texttt{0x00000000} & uDMA I2C Status register.\\
  \hline
  SETUP & \texttt{0x1A1021B4} & 32 & Config & R/W & \texttt{0x00000000} & uDMA I2C Configuration register.\\
  \hline
  \caption{uDMA I2C0}
\end{tabularx}
}


\regdoc{0x1A102180}{0x00000000}{RX\_SADDR}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{11}{\color{lightgray}\rule{\width}{\height}} \bitbox{5}{RX\_SADDR} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{RX\_SADDR}
  \end{bytefield}
}{
  \regitem{Bit 20 - 0}{RX\_SADDR}{R/W}{RX buffer base address bitfield:\\- Read: returns value of the buffer pointer until transfer is finished. Else returns 0.\\- Write: sets RX buffer base address}
}


\regdoc{0x1A102184}{0x00000000}{RX\_SIZE}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{12}{\color{lightgray}\rule{\width}{\height}} \bitbox{4}{RX\_SIZE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{RX\_SIZE}
  \end{bytefield}
}{
  \regitem{Bit 19 - 0}{RX\_SIZE}{R/W}{RX buffer size bitfield in bytes. (128kBytes maximum)\\- Read: returns remaining buffer size to transfer.\\- Write: sets buffer size.}
}


\regdoc{0x1A102188}{0x00000000}{RX\_CFG}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{9}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\tiny CLR} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~PENDING~}} \bitbox{1}{\tiny EN} \bitbox{3}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~CONTINOUS~}}
  \end{bytefield}
}{
  \regitem{Bit 6}{CLR}{W}{RX channel clear and stop transfer:\\-1'b0: disable\\-1'b1: stop and clear the on-going transfer}
  \regitem{Bit 5}{PENDING}{R}{RX transfer pending in queue status flag:\\-1'b0: no pending transfer in the queue\\-1'b1: pending transfer in the queue}
  \regitem{Bit 4}{EN}{R/W}{RX channel enable and start transfer bitfield:\\-1'b0: disable\\-1'b1: enable and start the transfer\\This signal is used also to queue a transfer if one is already ongoing.}
  \regitem{Bit 0}{CONTINOUS}{R/W}{RX channel continuous mode bitfield:\\-1'b0: disabled\\-1'b1: enabled\\At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer.}
}


\regdoc{0x1A102190}{0x00000000}{TX\_SADDR}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{11}{\color{lightgray}\rule{\width}{\height}} \bitbox{5}{TX\_SADDR} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TX\_SADDR}
  \end{bytefield}
}{
  \regitem{Bit 20 - 0}{TX\_SADDR}{R/W}{TX buffer base address bitfield:\\- Read: returns value of the buffer pointer until transfer is finished. Else returns 0.\\- Write: sets buffer base address}
}


\regdoc{0x1A102194}{0x00000000}{TX\_SIZE}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{12}{\color{lightgray}\rule{\width}{\height}} \bitbox{4}{TX\_SIZE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{TX\_SIZE}
  \end{bytefield}
}{
  \regitem{Bit 19 - 0}{TX\_SIZE}{R/W}{TX buffer size bitfield in bytes. (128kBytes maximum)\\- Read: returns remaining buffer size to transfer.\\- Write: sets buffer size.}
}


\regdoc{0x1A102198}{0x00000000}{TX\_CFG}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{9}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\tiny CLR} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~PENDING~}} \bitbox{1}{\tiny EN} \bitbox{3}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~CONTINOUS~}}
  \end{bytefield}
}{
  \regitem{Bit 6}{CLR}{W}{TX channel clear and stop transfer bitfield:\\-1'b0: disabled\\-1'b1: stop and clear the on-going transfer}
  \regitem{Bit 5}{PENDING}{R}{TX transfer pending in queue status flag:\\-1'b0: no pending transfer in the queue\\-1'b1: pending transfer in the queue}
  \regitem{Bit 4}{EN}{R/W}{TX channel enable and start transfer bitfield:\\-1'b0: disabled\\-1'b1: enable and start the transfer\\This signal is used also to queue a transfer if one is already ongoing.}
  \regitem{Bit 0}{CONTINOUS}{R/W}{TX channel continuous mode bitfield:\\-1'b0: disabled\\-1'b1: enabled\\At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer.}
}


\regdoc{0x1A1021A0}{0x00000000}{CMD\_SADDR}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{11}{\color{lightgray}\rule{\width}{\height}} \bitbox{5}{CMD\_SADDR} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{CMD\_SADDR}
  \end{bytefield}
}{
  \regitem{Bit 20 - 0}{CMD\_SADDR}{R/W}{CMD buffer base address bitfield:\\- Read: returns value of the buffer pointer until transfer is finished. Else returns 0.\\- Write: sets buffer base address}
}


\regdoc{0x1A1021A4}{0x00000000}{CMD\_SIZE}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{12}{\color{lightgray}\rule{\width}{\height}} \bitbox{4}{CMD\_SIZE} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{16}{CMD\_SIZE}
  \end{bytefield}
}{
  \regitem{Bit 19 - 0}{CMD\_SIZE}{R/W}{CMD buffer size bitfield in bytes. (128kBytes maximum)\\- Read: returns remaining buffer size to transfer.\\- Write: sets buffer size.}
}


\regdoc{0x1A1021A8}{0x00000000}{CMD\_CFG}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{9}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\tiny CLR} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~PENDING~}} \bitbox{1}{\tiny EN} \bitbox{3}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~CONTINOUS~}}
  \end{bytefield}
}{
  \regitem{Bit 6}{CLR}{W}{CMD channel clear and stop transfer bitfield:\\-1'b0: disabled\\-1'b1: stop and clear the on-going transfer}
  \regitem{Bit 5}{PENDING}{R}{CMD transfer pending in queue status flag:\\-1'b0: no pending transfer in the queue\\-1'b1: pending transfer in the queue}
  \regitem{Bit 4}{EN}{R/W}{CMD channel enable and start transfer bitfield:\\-1'b0: disabled\\-1'b1: enable and start the transfer\\This signal is used also to queue a transfer if one is already ongoing.}
  \regitem{Bit 0}{CONTINOUS}{R/W}{CMD channel continuous mode bitfield:\\-1'b0: disabled\\-1'b1: enabled\\At the end of the buffer transfer, the uDMA reloads the address / buffer size and starts a new transfer.}
}


\regdoc{0x1A1021B0}{0x00000000}{STATUS}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{13}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\tiny ACK} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~ARB\_LOST~}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~BUSY~}}
  \end{bytefield}
}{
  \regitem{Bit 2}{ACK}{R}{I2C ack flag, can be polling for busy:\\- 1'b0: ACK\\- 1'b1: NAK}
  \regitem{Bit 1}{ARB\_LOST}{R/W}{I2C arbitration lost status flag:\\- 1'b0: no error\\- 1'b1: arbitration lost error}
  \regitem{Bit 0}{BUSY}{R/W}{I2C bus busy status flag:\\- 1'b0: no transfer on-going\\- 1'b1: transfer on-going}
}


\regdoc{0x1A1021B4}{0x00000000}{SETUP}{
  \begin{bytefield}[endianness=big,bitwidth=2em]{16}
    \bitheader[lsb=16]{16-31} \\
    \bitbox{16}{\color{lightgray}\rule{\width}{\height}} \\[3ex]
    \bitheader{0-15} \\
    \bitbox{15}{\color{lightgray}\rule{\width}{\height}} \bitbox{1}{\let\bw=\width\resizebox{\bw}{!}{~DO\_RST~}}
  \end{bytefield}
}{
  \regitem{Bit 0}{DO\_RST}{R/W}{Reset command used to abort the on-going transfer and clear busy and arbitration lost status flags.}
}

